Memory technology implies the need for accessing data within memory devices, such as random access memory or other memory devices. Therefore, different addressing strategies have already been proposed.
Exemplarily for dynamic random access memory (DRAM) chips, data is stored well organized within arrays of rows and columns. This may be achieved using memory cells, organized as a matrix. Each memory block, e.g. each bit within the memory, may thus have a distinctive address. This address may be provided by a row address and a column address.
Accessing the rows and columns is possible using a row and column address, provided by respective signals via an addressing interface. The addressing interface provides a number of address terminals, e.g. connection pins, which number may correspond to the bandwidth of the address bus. For instance, a bit address bus with a bandwidth of 13 bit may be supported by 13 single address terminals of the memory device.
To select the respective memory blocks, address signals may be provided at the interface. The column may be addressed by a column address strobe (CAS). The row is addressed by a row address strobe (RAS).
For accessing the data, the central processing unit may provide via the addressing bus the row address strobe for selecting the correct row. After receiving the row address strobe, the respective row may be selected from the respective array within the memory device. The selected row may then be sensed from the array. There might be a delay for retrieving the row data from the memory. This time for reading the row and sensing the data and the delay may be called RAS-to-CAS-delay.
By providing the column address strobe after that, the respective column may be selected from the data buffer. The corresponding memory block, the piece of data which corresponds to the respective row and column within the memory, may thus be read from the memory and provided for further processing on a data bus.
In particular within dynamic random access memory (DRAM), data need to be refreshed after a while. Therefore, it is known to write data of a row, which has been cached in a cache, register, buffer or any other memory, back to the respective memory row within the memory device. This allows refreshing the memory.
A full read/write timing clock cycle for accessing memory may insofar include the time for transmitting the row address strobe, the time for the RAS-to-CAS-delay, the time for transmitting the column address strobe, and the time of the CAS-latency. The length of a read/write timing clock cycle may also depend on the clocking of the bus. One read/write timing clock cycle may only be expressed in integers of clocking intervals.
By multiplexing the RAS and CAS onto one interface, the number of pins may be reduced. Multiplexing may be understood as providing the RAS and CAS one after the other to the respective address terminals via the address bus. Nevertheless, the number of address terminals needs to correspond to the bandwidth of the address bus.
However, the number of pins at the address terminal is getting more critical, since new application designs require broader address bus bandwidth. Doubling the bandwidth of the address bus would require doubling the number of address terminals. As the package size of memory devices is required to be small, increasing the number of pins is hardly to implement.